Abstracting ESL Designs to UPPAAL System Models

ing ESL Designs to UPPAAL System Models Che-Wei Chang, Rainer Dömer Center for Embedded and Cyber-Physical Systems University of California, Irvine Irvine, CA 92697-2625, USA (949) 824-8919 cheweic,[email protected] http://www.cecs.uci.edu Technical Report CECS-14-13 November 21, 2014 Abstracting ESL Designs to UPPAAL System Modelsing ESL Designs to UPPAAL System Models Che-Wei Chang, Rainer Dömer Technical Report CECS-14-13 November 21, 2014 Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697-2625, USA (949) 824-8919 cheweic,[email protected] http://www.cecs.uci.edu Abstract Formal verification of system level models has been broadly studied to address the completeness concern that the simulation-based validation cannot cover. One approach among formal verification methods is to convert a system-level design into a well-defined representation and make use of existing formal verification tool to analyze the representation along with the properties of interest. In this report, we present an approach to convert an electronic system level (ESL) design in SpecC system level description language (SLDL) into an UPPAAL system level model which is an automaton network for formal verification purpose. Our approach does not only support most of the semantics in the behavioral hierarchy, but also the communication between modules such as event synchronization and most used predefined channels in SpecC semantics. Most important of all, our UPPAAL model can simulate the behaviors of traditional discrete event simulation (DES) and parallel discrete event simulation (PDES). The model can be used for May-Happen-in-Parallel analysis, and for design verification in other aspects, such as timing constraint and power consumption verification.Formal verification of system level models has been broadly studied to address the completeness concern that the simulation-based validation cannot cover. One approach among formal verification methods is to convert a system-level design into a well-defined representation and make use of existing formal verification tool to analyze the representation along with the properties of interest. In this report, we present an approach to convert an electronic system level (ESL) design in SpecC system level description language (SLDL) into an UPPAAL system level model which is an automaton network for formal verification purpose. Our approach does not only support most of the semantics in the behavioral hierarchy, but also the communication between modules such as event synchronization and most used predefined channels in SpecC semantics. Most important of all, our UPPAAL model can simulate the behaviors of traditional discrete event simulation (DES) and parallel discrete event simulation (PDES). The model can be used for May-Happen-in-Parallel analysis, and for design verification in other aspects, such as timing constraint and power consumption verification.